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| ? 2012 microchip technology inc. ds25160a-page 1 features: ? high psrr: >70 db @ 1 khz, typical ? 68.0 a typical quiescent current ? input operating voltage range: 3.6v to 16.0v ? 300 ma output current for all output voltages ? low dropout voltage, 300 mv typical @ 300 ma ? standard output voltage options (1.8v, 2.5v, 2.8v, 3.0v, 3.3v, 4.0v, 5.0v) ? output voltage range 1.8v to 5.5v in 0.1v increments (tighter increments are also possible per design) ? output voltage tolerances of 2.0% over entire temperature range ? stable with minimum 1.0 f output capacitance ? power good output ? shutdown input ? true current foldback protection ? short-circuit protection ? overtemperature protection applications: ? battery-powered devices ? battery-powered alarm circuits ? smoke detectors ?co 2 detectors ? pagers and cellular phones ? smart battery packs ? portable digital assistant (pda) ?digital cameras ? microcontroller power ? consumer products ? battery-powered data loggers related literature: ? an765, ?using microchip?s micropower ldos? (ds00765), microchip technology inc., 2007 ? an766, ?pin-compatible cmos upgrades to bipolar ldos? (ds00766), microchip technology inc., 2003 ? an792, ?a method to determine how much power a sot-23 can dissipate in an application? (ds00792), microchip technology inc., 2001 description: the mcp1755/1755s is a family of cmos low-dropout (ldo) voltage regulators that can deliver up to 300 ma of current while consuming only 68.0 a of quiescent current (typical). the input operating range is specified from 3.6v to 16.0v, making it an ideal choice for four to six primary cell battery-powered applications, 12v mobile applications and one to three cell li-ion- powered applications. the mcp1755/1755s is capable of delivering 300 ma with only 300 mv (typical) of input-to-output voltage differential. the output voltage tolerance of the mcp1755 is typically +0.85% at +25c and 2.0% maximum over the operating junction temperature range of -40c to +125c. line regulation is 0.01% typical at +25c. output voltages available for the mcp1755/1755s range from 1.8v to 5.5v. the ldo output is stable when using only 1 f of output capacitance. ceramic, tantalum or aluminum electrolytic capacitors may all be used for input and output. overcurrent limit and overtemperature shutdown provide a robust solution for any application. the mcp1755/1755s family has a true current foldback feature. when the load impedance decreases beyond the mcp1755/1755s load rating, the output current and voltage will gracefully foldback towards 30 ma at about 0v output. when the load impedance increases and returns to the rated load, the mcp1755/1755s will follow the same foldback curve as the device comes out of current foldback. package options for the mcp1755 include the sot-23-5, sot-223-5 and 8-lead 2 x 3 dfn. package options for the mcp1755s device include the sot-223-3 and 8-lead 2 x 3 dfn. 300 ma, 16v, high-performance ldo mcp1755/1755s
mcp1755/1755s ds25160a-page 2 ? 2012 microchip technology inc. package types ? mcp1755 package types ? mcp1755s 1 2 sot23-5 1 23 sot-223-5 4 5 shdn pwrgd gnd v out v in 4 3 5 pwrgd gnd v in v out shdn 2 x 3 dfn* ep-6 * includes exposed thermal pad (ep); see table 3-1 1 2 3 4 8 7 6 5 ep 9 nc nc shdn v in nc pwrgd gnd v out 12 sot-223-3 3 gnd v out v in 2 x 3 dfn* ep-4 * includes exposed thermal pad (ep); see table 3-2 1 2 3 4 8 7 6 5 ep 9 nc nc nc v in nc nc gnd v out ? 2012 microchip technology inc. ds25160a-page 3 mcp1755/1755s functional block diagrams + - v in v out gnd +v in error amplifier voltage reference over current over temperature mcp1755s mcp1755 ea + ? v out pmos r f c f i sns overtemperature v ref comp 92% of v ref t delay v in driver w/limit and shdn gnd soft-start sense undervoltage lock out v in reference shdn shdn shdn sensing (uvlo) pwrgd mcp1755/1755s ds25160a-page 4 ? 2012 microchip technology inc. typical application circuits c in 1f ceramic c out 1f ceramic v out 5.0v i out 30 ma v in v out 12v + gnd mcp1755s ? 2012 microchip technology inc. ds25160a-page 5 mcp1755/1755s 1.0 electrical characteristics absolute maximum ratings ? input voltage, v in .........................................................+17.6v v in , pwrgd, shdn ................. (gnd ? 0.3v) to (v in +0.3v) v out ................................................. (gnd ? 0.3v) to (+5.5v) internal power dissipation ............ internally-limited ( note 6 ) output short circuit current ................................. continuous storage temperature .....................................-55c to +150c maximum junction temperature ....................+165c( note 7 ) operating junction temperature...................-40c to +150c esd protection on all pins ?????????????? kv hbm and ? 400v mm ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ac/dc characteristics electrical specifications: unless otherwise specified, all limits are established for v in =v r +1v, note 1 , i load =1ma, c out = 1 f (x7r), c in = 1 f (x7r), t a =+25c, t r(vin) = 0.5 v/s, shdn =v in , pwrgd = 10k to v out . boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c. parameters sym. min. typ. max. units conditions input/output characteristics input operating voltage v in 3.6 ? 16.0 v output voltage operating range v out-range 1.8 ? 5.5 v input quiescent current i q ?68 100 a i l =0ma input quiescent current for shdn mode i shdn ?0.1 4 a shdn =gnd ground current i gnd ?300 400 a i load = 300 ma maximum output current i out_ma 300 ??ma output soft current limit scl ? 450 ? ma v out ? 0.1v, v in =v in(min) , current measured 10 ms after the load is applied output pulse current limit pcl ? 350 ? ma pulse duration < 100 ms, duty cycle < 50%, v out ? 0.1v, note 6 output short circuit foldback current i out_sc ?30?mav in =v in(min) , v out =gnd output voltage overshoot on start-up v over ?0.5?%v out v in =0 to 16v, i load = 300 ma note 1: the minimum v in must meet two conditions: v in ? 3.6v and v in ? v r + v dropout(max) . 2: v r is the nominal regulator output voltage when the input voltage v in =v rated +v dropout(max) or v in = 3.6v (whichever is greater); i out =1ma. 3: tcv out =(v out-high ?v out-low )x10 6 /(v r x ? temperature ), v out-high = highest voltage measured over the temperature range. v out-low = lowest voltage measured ov er the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-c ycle pulse testing. changes in output voltage due to heating effects are determined using thermal regulation specification tcv out . 5: dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of v in =v r +1v or v in = 3.6v (whichever is greater). 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operating j unction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact the device reliability. 7: the junction temperature is appr oximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough such t hat the rise in the junction temperature over the ambient temperature is not significant. 8: see section 4.6 ?shutdown input (shdn)? and figure 2-34 . mcp1755/1755s ds25160a-page 6 ? 2012 microchip technology inc. output voltage regulation v out v r ? 2.0% v r +0.85% v r +2.0 % v note 2 v out temperature coefficient tcv out ? 35 ppm/c note 3 line regulation ? v out / (v out x ? v in ) -0.05 0.01 +0.05 %/v v r +1v ? v in ? 16v load regulation ? v out /v out -0.5 0.1 +0.5 %i l = 1.0 ma to 300 ma, note 4 dropout voltage ( note 5 )v dropout ? 300 500 mv i l = 300 ma dropout current i do ?75 120 a v in =0.95v r , i out =0ma undervoltage lockout undervoltage lockout uvlo ? 3.0 ? v rising v in undervoltage lockout hysterisis uvlo hys ? 300 ? mv falling v in shutdown input logic high input v shdn-high 2.4 ?v in(max) v logic low input v shdn-low 0.0 ? 0.8 v shutdown input leakage current shdn ilk ?0.02 0.2 a shdn =16v power good output pwrgd input voltage operating range v pwrgd_vin 1.7 ?v in vi sink =1ma pwrgd threshold voltage (referenced to v out ) v pwrgd_th 90 92 94 %v out falling edge of v out pwrgd threshold hysteresis v pwrgd_hys ?2.0?%v out rising edge of v out pwrgd output voltage low v pwrgd_l ?0.2 0.45 vi pwrgd_sink = 5.0 ma, v out =0v pwrgd output sink current i pwrgd_l 5.0 ??mav pwrgd ? 0.45v ac/dc characteristics (continued) electrical specifications: unless otherwise specified, all limits are established for v in =v r +1v, note 1 , i load =1ma, c out = 1 f (x7r), c in = 1 f (x7r), t a =+25c, t r(vin) = 0.5 v/s, shdn =v in , pwrgd = 10k to v out . boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c. parameters sym. min. typ. max. units conditions note 1: the minimum v in must meet two conditions: v in ? 3.6v and v in ? v r + v dropout(max) . 2: v r is the nominal regulator output voltage when the input voltage v in =v rated +v dropout(max) or v in = 3.6v (whichever is greater); i out =1ma. 3: tcv out =(v out-high ?v out-low )x10 6 /(v r x ? temperature ), v out-high = highest voltage measured over the temperature range. v out-low = lowest voltage measured ov er the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. changes in output voltage due to heating effects are determined using thermal regulation specification tcv out . 5: dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of v in =v r +1v or v in = 3.6v (whichever is greater). 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operating j unction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact the device reliability. 7: the junction temperature is appr oximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough such t hat the rise in the junction temperature over the ambient temperature is not significant. 8: see section 4.6 ?shutdown input (shdn)? and figure 2-34 . ? 2012 microchip technology inc. ds25160a-page 7 mcp1755/1755s pwrgd leakage current i pwrgd_lk ?50 200 na v pwrgd pullup = 10 k ? to v in v in = 16v pwrgd time delay t pg ? 100 ? s rising edge of v out detect threshold to pwrgd active time delay t vdet_pwrgd ? 200 ? s falling edge of v out after transition from v out =v prwrgd_th +50mv to v pwrgd_th ?50 mv, r pullup =10k ? to v in ac performance output delay from v in to v out = 90% v reg t delay ?200?sv in =0v to 16v, v out =90% v r , t r(vin) =5v/s, output delay from v in to v out > 0.1v t delay_start ?80?sv in =0v to 16v, v out ? 0.1v, t r(vin) =5v/s, output delay from shdn ( note 8 ) t delay_shdn ?235?sv in =6v, v out =90%v r , v r =5v,s hdn = gnd to v in ?940?sv in =7v, v out =90%v r , v r =5v, s hdn = gnd to v in ?210?sv in =16v,v out =90%v r , v r =5v, s hdn = gnd to v in output noise e n ?0.3?v/( ? hz) i l =50ma, f=1khz, power supply ripple rejection ratio psrr ? 80 ? db v r =5v, f=1khz, i l = 100 ma, v inac =1v pk-pk , c in =0f, v in ? v r +1.5v ? 3.6v thermal shutdown temperature t sd ?150?c note 6 thermal shutdown hysteresis ? tsd ? 10 ? c ac/dc characteristics (continued) electrical specifications: unless otherwise specified, all limits are established for v in =v r +1v, note 1 , i load =1ma, c out = 1 f (x7r), c in = 1 f (x7r), t a =+25c, t r(vin) = 0.5 v/s, shdn =v in , pwrgd = 10k to v out . boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c. parameters sym. min. typ. max. units conditions note 1: the minimum v in must meet two conditions: v in ? 3.6v and v in ? v r + v dropout(max) . 2: v r is the nominal regulator output voltage when the input voltage v in =v rated +v dropout(max) or v in = 3.6v (whichever is greater); i out =1ma. 3: tcv out =(v out-high ?v out-low )x10 6 /(v r x ? temperature ), v out-high = highest voltage measured over the temperature range. v out-low = lowest voltage measured ov er the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-c ycle pulse testing. changes in output voltage due to heating effects are determined using thermal regulation specification tcv out . 5: dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of v in =v r +1v or v in = 3.6v (whichever is greater). 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operating j unction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact the device reliability. 7: the junction temperature is appr oximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough such t hat the rise in the junction temperature over the ambient temperature is not significant. 8: see section 4.6 ?shutdown input (shdn)? and figure 2-34 . mcp1755/1755s ds25160a-page 8 ? 2012 microchip technology inc. temperature specifications ( note 1 ) parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t j -40 ? +150 c storage temperature range t a -55 ? +150 c thermal package resistance thermal resistance, sot-223-3 ? ja ?62? c/w ? jc ?15? thermal resistance, sot-223-5 ? ja ?62? c/w ? jc ?15? thermal resistance, sot-23-5 ? ja ?256? c/w ? jc ?81? thermal resistance, 2 x 3 dfn-8 ? ja ?70? c/w ? jc ? 13.4 ? note 1: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact the device reliability. ? 2012 microchip technology inc. ds25160a-page 9 mcp1755/1755s 2.0 typical performance curves note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223. 2: junction temperature (t j ) is approximated by soaking t he device under test to an ambient temperature equal to the desired junction temperature. the test ti me is small enough such that the rise in junction temperatur e over the ambient temperature is not significant. figure 2-1: quiescent current vs. input voltage. figure 2-2: quiescent current vs. input voltage. figure 2-3: quiescent current vs. input voltage. figure 2-4: ground current vs. load current. figure 2-5: quiescent current vs. junction temperature. figure 2-6: output voltage vs. input voltage. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 30 40 50 60 70 80 90 100 s cent current (a) 0c +130c +25c -45c +90c 0 10 20 30 0246810121416 quie s input voltage (v) v out = 1.8v i out = 0 a 30 40 50 60 70 80 90 s cent current (a) -45c 0c +25c +90c +130c 0 10 20 0246810121416 quie s input voltage (v) v out = 3.3v i out = 0 a 30 40 50 60 70 80 90 s cent current (a) -45c 0c +25c +90c +130c 0 10 20 0246810121416 quie s input voltage (v) v out = 5.0v i out = 0 a 150 200 250 300 350 u nd current (a) v out = 1.8v v out = 5.0v v out = 3.3v 0 50 100 0 50 100 150 200 250 300 gro u load current (ma) 30 40 50 60 70 80 90 cent current (a) v out = 1.8v v out = 3.3v v out = 5.0v 0 10 20 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 quies junction temperature (c) 1.0 1.5 2.0 2.5 tput voltage (v) -45c 0c +25c +90c +130 c 0.0 0.5 0246810121416 ou input voltage (v) +130 c v out = 1.8v i out = 1 ma mcp1755/1755s ds25160a-page 10 ? 2012 microchip technology inc. note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223 figure 2-7: output voltage vs. input voltage. figure 2-8: output voltage vs. input voltage. figure 2-9: output voltage vs. load current. figure 2-10: output voltage vs. load current. figure 2-11: output voltage vs. load current. figure 2-12: dropout voltage vs. load current. 10 1.5 2.0 2.5 3.0 3.5 t put voltage (v) -45c 0c +25c +90c +130c 0.0 0.5 1 . 0 0246810121416 ou t input voltage (v) v out = 3.3v i out = 1 ma 2 3 4 5 6 t put voltage (v) -45c 0c +25c +90c +130c 0 1 0246810121416 ou t input voltage (v) v out = 5.0v i out = 1 ma 1.800 1.810 1.820 1.830 u tput voltage (v) +25c +130c +90c 0c -45c 1.780 1.790 0 50 100 150 200 250 300 o u load current (ma) v out = 1.8v v in = 3.6v 3.290 3.300 3.310 3.320 3.330 u tput voltage (v) +90c 0c -45c +130c +25c 3.270 3.280 0 50 100 150 200 250 300 o u load current (ma) v out = 3.3v v in = 4.3v 497 4.98 4.99 5.00 5.01 5.02 t put voltage (v) +25c +90c 0c -45c +130c 4.95 4.96 4 . 97 0 50 100 150 200 250 300 ou t load current (ma) v out = 5.0v v in = 6.0v 0.2 0.3 0.4 0.5 0.6 p out voltage (v) +25c +90c +130c v out = 3.3v 0 0.1 0 50 100 150 200 250 300 dro p load current (ma) 0c -45c ? 2012 microchip technology inc. ds25160a-page 11 mcp1755/1755s note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223 figure 2-13: dropout voltage vs. load current. figure 2-14: dynamic line response. figure 2-15: dynamic line response. figure 2-16: short circuit current vs. input voltage. figure 2-17: short circuit current vs. input voltage. figure 2-18: load regulation vs. temperature. 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 p out voltage (v) +130c +90c +25c v out = 5.0v 0.00 0.05 0.10 0.15 0 50 100 150 200 250 300 dro p load current (ma) -45c 0c 4.3v 5.3v v out =3.3v v in =4.3v to 5.3v i out =10 ma v out (ac coupled, 20 mv/div) time=10 s/div v in v in =4.3v to 5.3v i out =100 ma 5.3v 4.3v v in v out (ac coupled, 20 mv/div) time=10 s/div v out =3.3v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2 4 6 8 10 12 14 16 output current (a) input voltage (v) v out = 3.3v +25 c +125 c -40 c hard short circuit r out < 0.1 0.3 0.4 0.5 0.6 0.7 p ut current (a) soft short circuit r out = 5.5 v out = 3.3v +125c +25c -40c 0 0.1 0.2 2 4 6 8 10 12 14 16 out p input voltage (v) 0.10 0.15 0.20 0.25 0.30 0.35 0.40 d regulation (%) v in = 16v v in = 12v v in = 10v v in = 6v v in = 4.3v v in = 3.6v -0.05 0.00 0.05 -40 -25 -10 5 20 35 50 65 80 95 110 125 loa d temperature (oc) v out = 1.8v i out = 1 ma to 300 ma mcp1755/1755s ds25160a-page 12 ? 2012 microchip technology inc. note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223 figure 2-19: load regulation vs. temperature. figure 2-20: load regulation vs. temperature. figure 2-21: line regulation vs. temperature. figure 2-22: line regulation vs. temperature. figure 2-23: line regulation vs. temperature. figure 2-24: power supply ripple rejection vs. frequency. 005 0.10 0.15 0.20 0.25 0.30 0.35 0.40 d regulation (%) v in = 16v v in = 12v v in = 10v v in = 6v v in = 4.3v -0.10 -0.05 0.00 0 . 05 -40 -25 -10 5 20 35 50 65 80 95 110 125 loa d temperature (c) v out = 3.3v i out = 1 ma to 300 ma -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 -40 -25 -10 5 20 35 50 65 80 95 110 125 load regulation (%) temperature ( c) v out = 5.0v i out = 1 ma to 300 ma v in = 16v v in = 12v v in = 6v v in = 10v 0.015 0.020 0.025 0.030 0.035 0.040 0.045 regulation (%/v) v out = 1.8v 300 ma 150 ma 100 ma 50 ma 0 ma 0.000 0.005 0.010 -40 -25 -10 5 20 35 50 65 80 95 110 125 line temperature (c) 10 ma 0 005 0.010 0.015 0.020 0.025 0.030 regulation (%/v) v out = 3.3v 300 ma 150 ma 100 ma 50 ma 0 ma -0.005 0.000 0 . 005 -40 -25 -10 5 20 35 50 65 80 95 110 125 line temperature (c) 10 ma -0.01 0.00 0.01 0.01 0.02 0.02 0.03 0.03 -40 -25 -10 5 20 35 50 65 80 95 110 125 line regulation (%/v) temperature ( c) v out = 5.0v 300 ma 150 ma 100 ma 50 ma 10 ma 0 ma 100 -80 -60 -40 -20 0 psrr (db) v out = 1.8v v in = 4.1v v inac = 1vpk-pk c in = 0 f i out = 300 ma -140 -120 - 100 0.01 0.1 1 10 100 frequency (khz) i out = 10 ma ? 2012 microchip technology inc. ds25160a-page 13 mcp1755/1755s note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223 figure 2-25: power supply ripple rejection vs. frequency. figure 2-26: output noise vs. frequency (3 lines, v r = 1.8v, 3.3v, 5.0v). figure 2-27: start-up from v in . figure 2-28: start-up from shdn . figure 2-29: short circuit current foldback. figure 2-30: short circuit current foldback. 70 -60 -50 -40 -30 -20 -10 0 psrr (db) v out = 5.0v v in = 6.5v v inac = 1vpk-pk c in = 0 f i out = 10 ma i out = 300 ma -100 -90 -80 - 70 0.01 0.1 1 10 100 frequency (khz) i out 300 ma 0.100 1.000 10.000 u t noise (v/hz) c in = 1 f, c out = 1 f, i out = 50 ma v out = 1.8v v in = 3.6v v out = 50v 0.010 0.100 0.01 0.1 1 10 100 1000 outp u frequency (khz) v out 5 . 0v v in = 6.0v v out = 3.3v v in = 4.3v 4.3v 0v v in 3.3v 3.3v 0v 0v v out pwrgd time=80 s/div pwrgd=10k to v out i load =1 ma v in =0 to 4.3v v out =3.3v 4.3v 0v shdn 3.3v 3.3v 0v 0v v out pwrgd time=80 s/div pwrgd=10k to v out i load =1 ma v in =4.3v v out =3.3v 06 0.8 1.0 1.2 1.4 1.6 1.8 2.0 u tput voltage (v) v in = 3.6v v out = 1.8v 0.0 0.2 0.4 0 . 6 0 0.1 0.2 0.3 0.4 0.5 o u output current (a) increasing load decreasing load 10 1.5 2.0 2.5 3.0 3.5 t put voltage (v) v in = 4.3v v out = 3.3v 0.0 0.5 1 . 0 0 0.1 0.2 0.3 0.4 0.5 ou t output current (a) increasing load decreasing load mcp1755/1755s ds25160a-page 14 ? 2012 microchip technology inc. note 1: unless otherwise indicated v r =3.3v, c out = 1 f ceramic (x7r), c in = 1 f ceramic (x7r), i l =1ma, t a =+25c, v in =v r +1v or v in = 3.6v (whichever is greater), shdn =v in , package = sot-223 figure 2-31: short circuit current foldback. figure 2-32: dynamic load response. figure 2-33: dynamic load response. figure 2-34: start-up delay from shdn to 90% v out . 2.0 3.0 4.0 5.0 6.0 u tput voltage (v) v in = 6.0v v out = 5.0v 0.0 1.0 0 0.1 0.2 0.3 0.4 0.5 o u output current (a) increasing load decreasing load v out (ac coupled, 200 mv/div) i out (200 ma/div) time=20 s/div v out =3.3v i out =100 a to 300 ma v out (ac coupled, 200 mv/div) i out (200 ma/div) time=20 s/div v out =3.3v i out =1 ma to 300 ma 300 400 500 600 700 800 900 1000 p delay time (s) +25 c -20 c +90 c v out = 5.0v 0 100 200 300 6 8 10 12 14 16 startu p input voltage (v) +125 c -40 c ? 2012 microchip technology inc. ds25160a-page 15 mcp1755/1755s 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 and table 3-2 . 3.1 regulated output voltage (v out ) connect v out to the positive side of the load and the positive side of the output capacitor. the positive side of the output capacitor should be physically located as close to the ldo v out pin as is practical. the current flowing out of this pin is equal to the dc load current. 3.2 power good output (pwrgd) the pwrgd output is an open-drain output used to indicate when the ldo output voltage is within 92% (typically) of its nominal regulation value. the pwrgd threshold has a typical hysteresis value of 2%. the pwrgd output is delayed by 100 s (typical) from the time the ldo output is within 92% + 3% (maximum hysteresis) of the regulated output value on power-up. this delay time is internally fixed. the pwrgd pin may be pulled up to v in or v out . pulling up to v out conserves power when the device is in shutdown (shdn =0v) mode. 3.3 ground terminal (gnd) regulator ground. tie gnd to the negative side of the output capacitor and also to the negative side of the input capacitor. only the ldo bias current flows out of this pin; there is no high current. the ldo output regulation is referenced to this pin. minimize voltage drops between this pin and the negative side of the load. 3.4 shutdown input (shdn ) the shdn input is used to turn the ldo output voltage on and off. when the shdn input is at a logic-high level, the ldo output voltage is enabled. when the shdn input is pulled to a logic-low level, the ldo output voltage is disabled. when the shdn input is pulled low, the pwrgd output also goes low and the ldo enters a low quiescent current shutdown state. table 3-1: mcp1755 pin function table sot-223-5 sot-23-5 2 x 3 dfn name function 451v out regulated voltage output 5 4 2 pwrgd open drain power good output ? ? 3, 6, 7 nc no connection 3 2 4 gnd ground terminal 1 3 5 shdn shutdown input 218v in unregulated supply voltage 6 ? 9 ep exposed pad, connected to gnd table 3-2: mcp1755s pin function table sot-223-3 2 x 3 dfn name function 31v out regulated voltage output ? 2, 3, 5, 6, 7 nc no connection 2 4 gnd ground terminal 18v in unregulated supply voltage 4 9 ep exposed pad, connected to gnd mcp1755/1755s ds25160a-page 16 ? 2012 microchip technology inc. 3.5 unregulated input voltage (v in ) connect v in to the input unregulated source voltage. like all low dropout linear regulators, low source impedance is necessary for the stable operation of the ldo. the amount of capacitance required to ensure low source impedance will depend on the proximity of the input source capacitors or battery type. for most applications, 1 f of capacitance will ensure stable operation of the ldo circuit. the input capacitor should have a capacitance value equal to or larger than the output capacitor for performance applications. the input capacitor will supply the load current during transients and improve performance. for applications that have load currents below 10 ma, the input capacitance requirement can be lowered. the type of capacitor used may be ceramic, tantalum or aluminum electrolytic. the low esr characteristics of the ceramic will yield better noise and psrr performance at high frequency. 3.6 exposed pad (ep) some of the packages have an exposed metal pad on the bottom of the package. the exposed metal pad gives the device better thermal characteristics by providing a good thermal path to either the pcb or heatsink to remove heat from the device. the exposed pad of the package is internally connected to gnd. ? 2012 microchip technology inc. ds25160a-page 17 mcp1755/1755s 4.0 device overview the mcp1755/1755s is a 300 ma output current, low- dropout (ldo) voltage regulator. the low-dropout voltage of 300 mv typical at 300 ma of current makes it ideal for battery-powered applications. the input voltage range is 3.6v to 16.0v. unlike other high output current ldos, the mcp1755/1755s typically draws only 300 a of quiescent current for a 300 ma load. the mcp1755 adds a shutdown control input pin and a power good output pin. the output voltage options are fixed. 4.1 ldo output voltage the mcp1755 ldo has a fixed output voltage. the output voltage range is 1.8v to 5.5v. the mcp1755s ldo is available as a fixed voltage device. 4.2 output current and current limiting the mcp1755/1755s ldo is tested and ensured to supply a minimum of 300 ma of output current. the mcp1755/1755s has no minimum output load, so the output load current can go to 0 ma and the ldo will continue to regulate the output voltage to within tolerance. the mcp1755/1755s also incorporates a true output current foldback. if the output load presents an excessive load due to a low-impedance short circuit condition, the output current and voltage will fold back towards 30 ma and 0v, respectively. the output voltage and current will resume normal levels when the excessive load is removed. if the overload condition is a soft overload, the mcp1755/1755s will supply higher load currents of up to typically 350 ma. this allows for device usage in applications that have pulsed load currents having an average output current value of 300 ma or less. output overload conditions may also result in an overtemperature shutdown of the device. if the junction temperature rises above +150c (typical), the ldo will shut down the output. see section 4.8, overtemperature protection for more information on overtemperature shutdown. figure 4-1: typical current foldback. 4.3 output capacitor the mcp1755/1755s requires a minimum output capacitance of 1 f for output voltage stability. ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. aluminum-electrolytic and tantalum capacitors can be used on the ldo output as well. the equivalent series resistance (esr) of the electrolytic output capacitor should be no greater than 2 ohms. the output capacitor should be located as close to the ldo output as is practical. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. a typical 1 f x7r 0805 capacitor has an esr of 50 milli-ohms. larger ldo output capacitors can be used with the mcp1755/1755s to improve dynamic performance and power supply ripple rejection performance. a maximum of 1000 f is recommended. aluminum- electrolytic capacitors are not recommended for low temperature applications of < -25c. 4.4 input capacitor low input source impedance is necessary for the ldo output to operate properly. when operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f is recommended for most applications. for applications that have output step load requirements, the input capacitance of the ldo is very important. the input capacitance provides the ldo with a good local low-impedance source to pull the transient currents from, in order to respond quickly to the output load step. for good step response performance, the input capacitor should be of equivalent or higher value than the output capacitor. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will also help reduce any high-frequency noise on the input and output of the ldo and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the ldo. 2.0 3.0 4.0 5.0 6.0 u tput voltage (v) v in = 6.0v v out = 5.0v 0.0 1.0 0 0.1 0.2 0.3 0.4 0.5 o u output current (a) increasing load decreasing load mcp1755/1755s ds25160a-page 18 ? 2012 microchip technology inc. 4.5 power good output (pwrgd) the open drain pwrgd output is used to indicate when the output voltage of the ldo is within 92% (typical value, see section 1.0 ?electrical characteristics? for minimum and maximum specifications) of its nominal regulation value. as the output voltage of the ldo rises, the open-drain pwrgd output will actively be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. once this threshold has been exceeded, the power good time delay is started (shown as t pg in the ac/dc characteristics table). the power good time delay is fixed at 100 s (typical). after the time delay period, the pwrgd open-drain output becomes inactive and may be pulled high by an external pullup resistor, indicating that the output voltage is stable and within regulation limits. the power good output is typically pulled up to v in or v out . pulling the signal up to v out conserves power during shutdown mode. if the output voltage of the ldo falls below the power good threshold, the power good output will transition low. the power good circuitry has a 200 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. see figure 4-2 for power good timing characteristics. when the ldo is put into shutdown mode using the shdn input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. the timing diagram for the power good output when using the shutdown input is shown in figure 4-3 . the power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the ldo input voltage. this output is capable of sinking a minimum of 5 ma (v pwrgd <0.45v). figure 4-2: power good timing. figure 4-3: power good timing from shutdown. 4.6 shutdown input (shdn ) the shdn input is an active-low input signal that turns the ldo on and off. the shdn threshold is a fixed voltage level. the minimum value of this shutdown threshold required to turn the output on is 2.4v. the maximum value required to turn the output off is 0.8v. the shdn input will ignore low-going pulses (pulses meant to shut down the ldo) that are up to 400 ns in pulse width. if the shutdown input is pulled low for more than 400 ns, the ldo will enter shutdown mode. this small bit of filtering helps to reject any system noise spikes on the shutdown input signal. on the rising edge of the shdn input, the shutdown circuitry has a 135 s delay before allowing the ldo output to turn on. this delay helps to reject any false turn-on signals or noise on the shdn input signal. after the 135 s delay, the ldo output enters its soft-start period as it rises from 0v to its final regulation value. if the shdn input signal is pulled low during the 135 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the shdn input. the total time from the shdn input going high (turn-on) to the ldo output being in regulation is typically 235 s. see figure 4-4 for a timing diagram of the shdn input. t pg tv det_pwrgd v pwrgd_th v out pwrgd v ol v oh v in shdn v out t delay_shdn pwrgd t pg c load =1.0f ? 2012 microchip technology inc. ds25160a-page 19 mcp1755/1755s figure 4-4: shutdown input timing diagram. 4.7 dropout voltage and undervoltage lockout dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a v r + 1.0v differential applied. the mcp1755/1755s ldo has a very low dropout voltage specification of 300 mv (typical) at 300 ma of output current. see section 1.0 ?electrical characteristics? for maximum dropout voltage specifications. the mcp1755/1755s ldo operates across an input voltage range of 3.6v to 16.0v and incorporates input undervoltage lockout (uvlo) circuitry that keeps the ldo output voltage off until the input voltage reaches a minimum of 3.00v (typical) on the rising edge of the input voltage. as the input voltage falls, the ldo output will remain on until the input voltage level reaches 2.70v (typical). for high-current applications, voltage drops across the pcb traces must be taken into account. the trace resistances can cause significant voltage drops between the input voltage source and the ldo. for applications with input voltages near 3.0v, these pcb trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. 4.8 overtemperature protection the mcp1755/1755s ldo has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately +150 c. if the ldo junction temperature does reach +150 c, the ldo output will be turned off until the junction temperature cools to approximately +140 c, at which point the ldo output will automatically resume normal operation. if the internal power dissipation continues to be excessive, the device will again shut off. the junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. see section 5.0 ?application circuits and issues? for more information on ldo power dissipation and junction temperature. shdn v out 135 s t delay_shdn 400 ns (typical) c load = 1.0 f mcp1755/1755s ds25160a-page 20 ? 2012 microchip technology inc. notes: ? 2012 microchip technology inc. ds25160a-page 21 mcp1755/1755s 5.0 application circuits and issues 5.1 typical application the mcp1755/1755s is most commonly used as a voltage regulator. the low quiescent current and low dropout voltage make it ideal for many battery-powered applications. figure 5-1: typical application circuit. 5.1.1 application input conditions 5.2 power calculations 5.2.1 power dissipation the internal power dissipation of the mcp1755/1755s is a function of input voltage, output voltage and output current. the power dissipation, as a result of the quiescent current draw, is so low, it is insignificant (68.0 a x v in ). the following equation can be used to calculate the internal power dissipation of the ldo. equation 5-1: the maximum continuous operating junction temperature specified for the mcp1755/1755s is +150 c . to estimate the internal junction temperature of the mcp1755/1755s, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (r ? ja ). the thermal resistance from junction to ambient for the sot-23 package is estimated at 336 c/w. equation 5-2: the maximum power dissipation capability for a package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient temperature for the application. the following equation can be used to determine the package maximum internal power dissipation. equation 5-3: equation 5-4: equation 5-5: package type = sot-23 input voltage range = 3.6v to 4.8v v in maximum = 4.8v v out typical = 1.8v i out = 50 ma maximum gnd v out v in c in 1f ceramic c out 1f ceramic v out v in 3.6v to 4.8v 1.8v i out 50 ma mcp1755s p ldo v in max ? ?? v out min ?? ? ?? i out max ? ?? ? = p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage t jmax ?? p total r ? ja ? t amax + = t j(max) = maximum continuous junction temperature p total = total device power dissipation r ? ja = thermal resistance from junction to ambient t amax = maximum ambient temperature p dmax ?? t jmax ?? t amax ?? ? ?? r ? ja --------------------------------------------------- = p d(max) = maximum device power dissipation t j(max) = maximum continuous junction temperature t a(max) = maximum ambient temperature r ? ja = thermal resistance from junction to ambient t jrise ?? p dmax ?? r ? ja ? = t j(rise) = rise in device junction temperature over the ambient temperature p d(max) = maximum device power dissipation r ? ja = thermal resistance from junction to ambient t j t jrise ?? t a + = t j = junction temperature t j(rise) = rise in device junction temperature over the ambient temperature t a = ambient temperature mcp1755/1755s ds25160a-page 22 ? 2012 microchip technology inc. 5.3 voltage regulator internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. the power dissipation, as a result of ground current, is small enough to be neglected. example 5-1: power dissipation 5.3.1 device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. the thermal resistance from junction to ambient (r ? ja ) is derived from an eia/jedec standard for measuring thermal resistance for small surface mount packages. the eia/ jedec specification is jesd51-7, ?high effective thermal conductivity test board for leaded surface mount packages? . the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. refer to an792, ? a method to determine how much power a sot-23 can dissipate in an application? (ds00792), for more information regarding this subject. example 5-2: 5.3.2 junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below. example 5-3: maximum package power dissipation examples at +40c ambient temperature 5.4 voltage reference the mcp1755/1755s can be used not only as a regulator, but also as a low quiescent current voltage reference. in many microcontroller applications, the initial accuracy of the reference can be calibrated using production test equipment or by using a ratio measurement. when the initial accuracy is calibrated, the thermal stability and line regulation tolerance are the only errors introduced by the mcp1755/1755s ldo. the low-cost, low quiescent current and small ceramic output capacitor are all advantages when using the mcp1755/1755s as a voltage reference. figure 5-2: using the mcp1755/1755s as a voltage reference. package package type = sot-23 input voltage v in = 3.6v to 4.8v ldo output voltages and currents v out = 1.8v i out =50ma maximum ambient temperature t a(max) = +40c internal power dissipation internal power dissipation is the product of the ldo output current times the voltage across the ldo (v in to v out ). p ldo(max) =(v in(max) ?v out(min) )xi out(max) p ldo = (4.8v ? (0.97 x 1.8v)) x 50 ma p ldo =152.7mw t j(rise) =p total xr ? ja t jrise = 152.7 mw x 336.0 c/watt t jrise =51.3 c t j =t jrise +t a(max) t j =91.3c sot-23 (336.0c/watt = r ? ja ) p d(max) = (125c ? 40c)/336c/w p d(max) =253mw sot-89 (153.3c/watt = r ? ja ) p d(max) = (125c ? 40c)/153.3c/w p d(max) =554mw pic ? gnd v in c in 1f c out 1f bridge sensor v out v ref ado ad1 ratio metric reference 68 a bias microcontroller mcp1755s ? 2012 microchip technology inc. ds25160a-page 23 mcp1755/1755s 5.5 pulsed load applications for some applications, there are pulsed load current events that may exceed the specified 300 ma maximum specification of the mcp1755/1755s. the internal current limit of the mcp1755/1755s will prevent high peak load demands from causing non- recoverable damage. the 300 ma rating is a maximum average continuous rating. as long as the average current does not exceed 300 ma, higher pulsed load currents can be applied to the mcp1755/1755s . the typical foldback current limit for the mcp1755/1755s is 350 ma (t a =+25c). mcp1755/1755s ds25160a-page 24 ? 2012 microchip technology inc. notes: ? 2012 microchip technology inc. ds25160a-page 25 mcp1755/1755s 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3-lead sot-223 (mcp1755s only) example: 5-lead sot-223 (mcp1755 only) example: part number first line code mcp1755s-1802e/db 1755s18 mcp1755st-1802e/db 1755s18 mcp1755s-3302e/db 1755s33 mcp1755st-3302e/db 1755s33 mcp1755s-5002e/db 1755s50 mcp1755st-5002e/db 1755s50 part number first line code mcp1755t-1802e/dc 175518 mcp1755t-3302e/dc 175533 mcp1755t-5002e/dc 175550 5-lead sot-23 (mcp1755 only) example: part number code mcp1755t-1802e/ot 2snn mcp1755t-3302e/ot 3cnn mcp1755t-5002e/ot 3dnn 1755s 18 edby1240 256 1755 18 edcy1240 256 2s25 mcp1755/1755s ds25160a-page 26 ? 2012 microchip technology inc. package marking information (continued) 8-lead dfn (2x3) example: part number first line code mcp1755-1802e/mc alz mcp1755t-1802e/mc alz mcp1755-3302e/mc aka mcp1755t-3302e/mc aka mcp1755-5002e/mc akb mcp1755t-5002e/mc akb mcp1755s-1802e/mc ama mcp1755st-1802e/mc ama mcp1755s-3302e/mc amb mcp1755st-3302e/mc amb mcp1755s-5002e/mc amc mcp1755st-5002e/mc amc alz 240 256 ? 2012 microchip technology inc. ds25160a-page 27 mcp1755/1755s !" ! #$! !% # $ !% # $ #&! ! !# "' ( )*+ ) # & #, $ --# $## . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / 3# 44" " 4 # 5 56 7 5$ 8 %4 ! 5 4 !1# )* 6$# !4 !1# 9)* 6, : # ; ; < # ! %% ; !!1 / : # ( 9 6, =!# " 9 !!1 / =!# " ( 6, 4# 9 9( 9 4 ! / ( 4 !=!# 8 9 9 < 84 !=!# 8 . #4# 4 ( ; ; 4 ! > ; > d b2 e e1 1 2 3 e e1 a a2 a1 b c l - * ) mcp1755/1755s ds25160a-page 28 ? 2012 microchip technology inc. . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / ? 2012 microchip technology inc. ds25160a-page 29 mcp1755/1755s !" ! #$! !% # $ !% # $ #&! ! !# "' ( )*+ ) # & #, $ --# $## . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / 3# 44" " 4 # 5 56 7 5$ 8 %4 ! 5 ( 4 !1# )* 6$# !4 !1# (<)* 6, : # ; ; < # ! %% 9 !!1 / : # (( 9 9( 6, =!# " 9<9 9 !!1 / =!# " ( ( (( 6, 4# 9( 9( 9(( 4 ! / < 4 !=!# 8 ( ( 84 !=!# 8 ( ( . #4# 4 ; 4 ! > > <> d b2 e e1 1 2 34 n e e1 a2 a b a1 c l - * ) mcp1755/1755s ds25160a-page 30 ? 2012 microchip technology inc. . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / ? 2012 microchip technology inc. ds25160a-page 31 mcp1755/1755s !" ! #$! !% # $ !% # $ #&! ! !# "' ( )*+ ) # & #, $ --# $## . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / 3# 44" " 4 # 5 56 7 5$ 8 %1 5 ( 4 !1# ()* 6$# !4 !1# )* 6, : # ; ( !!1 / / < ; # ! %% ; ( 6, =!# " ; !!1 / =!# " ; < 6, 4# ; . #4# 4 ; 9 . # # 4 ( ; < . # > ; > 4 ! / < ; 9 4 !=!# 8 ; ( n b e e1 d 1 2 3 e e1 a a1 a2 c l l1 - * ) mcp1755/1755s ds25160a-page 32 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012 microchip technology inc. ds25160a-page 33 mcp1755/1755s 1 , $ !&% #$ , 08$# $ #8 #!-# # # ! 1 / , & !#8 #! 1 / - $ #! !# "' ( )*+ ) # & #, $ --# $## ".+ % 0$ $ -# $## 0% % # $ . # #$ # / ! - 0 # 1 / % # #! # ## +22--- 2 / 3# 44" " 4 # 5 56 7 5$ 8 %1 5 < 1# ()* 6, : # < # ! %% ( * # # / ". 6, 4# )* 6, =!# " )* "& !1 !4# ; (( "& !1 !=!# " ( ; ( * # #=!# 8 ( * # #4# 4 ( * # ## "& !1 ! ? ; ; d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view - * * mcp1755/1755s ds25160a-page 34 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2012 microchip technology inc. ds25160a-page 35 mcp1755/1755s appendix a: revision history revision a (december 2012) ? original release of this document. mcp1755/1755s ds25160a-page 36 ? 2012 microchip technology inc. notes: ? 2012 microchip technology inc. ds25160a-page 37 mcp1755/1755s product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp1755: 300 ma, 16v, high-performance ldo mcp1755t: 300 ma, 16v, high-performance ldo (tape and reel) mcp1755s: 300 ma, 16v, high-performance ldo mcp1755st: 300 ma, 16v, high-performance ldo (tape and reel) tape and reel: t = tape and reel output voltage*: 18 = 1.8v ?standard? 33 = 3.3v ?standard? 50 = 5.0v ?standard? *contact factory for other voltage options extra feature code: 0 = fixed tolerance: 2 = 2% (standard) temperature range: e = -40c to +125c package: db = plastic small outline (sot-223), 3-lead dc = plastic small outline (sot-223), 5-lead ot = plastic small outline (sot-23), 5-lead mc = plastic dual flat, no lead (2x3 dfn), 8-lead part no. x- x x package tape and reel device x/ temp. x tolerance x feature code xx output voltage examples: a) mcp1755st-1802e/db: tape and reel, 1.8v output voltage, fixed, 2% tolerance, 3ld sot-223 package. b) mcp1755st-3302e/db: tape and reel, 3.3v output voltage, fixed, 2% tolerance, 3ld sot-223 package. c) mcp1755st-5002e/db: tape and reel, 5.0v output voltage, fixed, 2% tolerance, 3ld sot-223 package. a) mcp1755t-1802e/dc: tape and reel, 1.8v output voltage, fixed, 2% tolerance, 5ld sot-223 package b) mcp1755t-3302e/dc: tape and reel, 3.3v output voltage, fixed, 2% tolerance, 5ld sot-223 package c) mcp1755t-5002e/dc: tape and reel, 5.0v output voltage, fixed, 2% tolerance, 5ld sot-223 package a) mcp1755t-1802e/ot: tape and reel, 1.8v output voltage, fixed, 2% tolerance, 5ld sot-23 package b) mcp1755t-3302e/ot: tape and reel, 3.3v output voltage, fixed, 2% tolerance, 5ld sot-23 package c) mcp1755t-5002e/ot: tape and reel, 5.0v output voltage, fixed, 2% tolerance, 5ld sot-23 package a) mcp1755t-1802e/mc: tape and reel, 1.8v output voltage, fixed, 2% tolerance, 8ld 2x3 dfn package b) mcp1755t-3302e/mc: tape and reel, 3.3v output voltage, fixed, 2% tolerance, 8ld 2x3 dfn package c) mcp1755t-5002e/mc: tape and reel, 5.0v output voltage, fixed, 2% tolerance, 8ld 2x3 dfn package a) mcp1755st-1802e/mc: tape and reel, 1.8v output voltage, fixed, 2% tolerance, 8ld 2x3 dfn package range mcp1755/1755s ds25160a-page 38 ? 2012 microchip technology inc. notes: ? 2012 microchip technology inc. ds25160a-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620768181 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds25160a-page 40 ? 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